Alec Wyen

Firmware & Systems Engineering | BIOS, Embedded Systems, and Emerging Memory

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Professional Summary

Engineering Manager and Principal Firmware Engineer with 12+ years of experience spanning BIOS/UEFI development, embedded systems, DRAM/memory technologies, and silicon enablement.
Currently leading Micron Technology’s BIOS Development team, managing six engineers across x86 and ARM platforms.
Experienced in automation strategies, team leadership, mentoring, and delivering production-ready firmware features.

Work Experience

Principal Engineering Lead, BIOS Development – Micron Technology

Sept 2024 – Present | Boise, ID

  • Lead a cross-platform BIOS development team of six engineers, spanning Intel, AMD, and ARM platforms.
  • Define team strategy, pillars, and long-term roadmap to improve reliability and accelerate feature releases.
  • Champion automation initiatives for end-to-end build, test, and release pipelines.
  • Mentor engineers in technical growth, career development, and cross-team collaboration.

Senior BIOS/Firmware Engineer – Micron Technology

Oct 2023 – Sept 2024 | Boise, ID

  • Delivered bi-weekly BIOS feature updates for Intel Raptor Lake and Birch Stream platforms.
  • Reviewed and provided feedback on peer code commits across Server and Client BIOS repositories.
  • Developed BIOS features supporting Characterization, Enablement, and Validation teams.
  • Implemented RMT Temperature Drift Automation and DRAM Design ID reporting to streamline workflows.
  • Published internal standards for BIOS code changes and version numbers to improve team understanding.
  • Standardized BIOS release notes format, incorporating stakeholder feedback for clarity and accessibility.

Senior Product Engineer – DRAM Node Development Tactical Team Lead

Mar 2023 – Oct 2023 | Boise, ID

  • Led a team of five engineers on special Node Development projects supporting critical DEGT needs.
  • Directed project priorities, assigned tasks, and managed individual performance using JIRA.
  • Reported weekly status updates to Product Engineering leadership on tactical projects and milestones.
  • Executed individual contributor tasks focused on 1γ CMOS short-loop experimentation to shorten learning cycles.

Senior Product Engineer – Emerging Memory Node Development Team Lead

Nov 2021 – Mar 2023 | Boise, ID

  • Promoted to Senior Engineer and appointed team leader for 20-series emerging memory projects.
  • Led a team of three engineers to achieve spider-chip functional milestones ahead of schedule.
  • Delivered daily progress updates and recommendations to stakeholders during PI, YE, and PE meetings.
  • Presented bi-weekly executive summaries to division Senior Vice President and staff.
  • Coordinated knowledge transfer from Boise to Japan to facilitate Fab 15 production ramp.
  • Partnered with DRAM Node Development teams to adapt high-volume best known methods (BKMs) to emerging memory.
  • Mentored team members, provided coaching, and guided career growth toward subject matter expertise.

Product Engineer – Emerging Memory Spider Chip Project Lead

Oct 2020 – Nov 2021 | Boise, ID

  • Produced documentation tracking changes from parent design and led training sessions for engineers.
  • Represented Product Engineering priorities and timelines to Process Integration, Yield Enhancement, and Probe Test teams.
  • Monitored production line incoming lots, ensuring experiment intentions were understood before testing.
  • Defined and monitored probe wafer test conditions for adequate coverage.
  • Analyzed silicon experiment data and summarized results in lot reports to drive process improvements.
  • Partnered with Yield Enhancement engineers to identify and track defects through physical failure analysis.

Product Engineer – Emerging Memory Node Development

Sept 2017 – Oct 2020 | Boise, ID

  • Performed statistical analysis on probe lots using JMP and Python, providing feedback to Process Integration teams.
  • Characterized array defects for physical failure analysis submissions.
  • Developed electrical failure analysis techniques with Hamamatsu iPhemos Emissions Testers.
  • Created Python scripts to map logical addresses to physical cell locations for layout sensitivity, sense-amp, and routing analysis.
  • Designed an automated routing-to-cell interaction analyzer using OpenCV and multiprocessing.
  • Verified pre-silicon RAS chain timing and power supply operation with Cadence Virtuoso and Verilog simulations.
  • Validated post-silicon RAS chain timing using microprobing techniques.
  • Led Training Taskforce to improve new-hire productivity and created a JIRA new-hire checklist.
  • Consolidated tools across EM departments into a shared Bitbucket repository to reduce duplicate development.

Product Engineer – Hybrid Memory Cube Product Engineering

May 2013 – Sept 2017 | Boise, ID

  • Designed and developed HMC DRAM Built-In-Self-Test code for defect detection and field repair.
  • Co-authored an internal white-paper on HMC self-test capabilities and self-modifying code.
  • Produced field-deployable firmware patches for customer-specific issues.
  • Developed Python scripts to model firmware code size against DRAM repair storage needs.
  • Collaborated with Test Engineers to update production test flows for firmware releases.
  • Debugged customer RMAs and fed results back to process improvement teams.
  • Trained Quality Engineers in RMA procedures and developed a web interface for reporting process improvements.
  • Modeled HMC repair densities to estimate yield and define quality cut-offs.

Electrical Engineering Intern – Digilent Inc.

Jan 2012 – May 2013 | Pullman, WA

Education

Washington State University — B.S., Computer Engineering
Pullman, WA

Technical Skills

  • Languages & Systems: C, C++, Python, Assembly, HTML/CSS, JavaScript, Django, SQLite
  • Firmware & Platforms: BIOS/UEFI, Intel & ARM platforms, Embedded Systems, Device Drivers
  • Protocols: UART, I2C, SPI
  • Tools: JIRA, Confluence, Git/Bitbucket, JMP, Cadence Virtuoso, OpenCV
  • Domains: DRAM, Emerging Memories, Electrical Failure Analysis, Statistical Data Analysis, Test Automation

Professional Interests

Leadership Development • Engineering Management • Firmware & Microcode • Embedded Systems • Emerging Memory Technologies • Software Tool Development